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RD-19230
16-BIT MONOLITHIC TRACKING RESOLVER-TO-DIGITAL CONVERTER
FEATURES
* Accuracy up to 1.3 Arc Minutes * Internal Synthesized Reference * +5 Volt Only Option * Programmable Resolution, Dual Bandwidth and Tracking Rate * Internal Encoder Emulation with Independent Resolution Control * Differential Resolver Input Mode * Velocity Output Eliminates Tachometer * Built-In-Test (BIT) Output, No 180 Hangup with AC Reference
DESCRIPTION
The RD-19230 is a small and versatile, low cost, state-of-the-art 16bit monolithic Resolver-to-Digital Converter. This single chip converter offers programmable features such as resolution, bandwidth, velocity output scaling and encoder emulation. .com Resolution programming allows selection of 10, 12, 14, or 16 bit, with accuracies to 1.3 minutes. The parallel digital data and the internal encoder emulation signals (A QUAD B) have independent resolution control. Internal encoder emulation will permit inhibiting (freezing) the parallel digital data without interrupting the A and B outputs. The internal Synthesized Reference section eliminates errors due to quadrature voltage and ensures operation with a rotor-to-stator phase shift of up to 45 degrees. The velocity output (VEL) can be used in place of a tachometer. It has a range of 4 V relative to analog ground. The velocity scale factor/tracking rate is programmed with a single resistor. This converter provides the option of using a second set of filter components which can be used in dual bandwidth or switch on the fly applications.
* -40 to +85C Operating Temperature * Programmable for LVDT Input
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APPLICATIONS
With its low cost, small size, high accuracy, and versatile performance, the RD-19230 converter is ideal for use in modern high performance industrial control systems. It is ideal for users who wish to use a resolver input in their encoder based system. Typical applications include motor control, machine tool control, robotics, and process control.
FOR MORE INFORMATION CONTACT:
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Data Device Corporation 105 Wilbur Place Bohemia, New York 11716 631-567-5600 Fax: 631-567-7358 www.ddc-web.com
Technical Support: 1-800-DDC-5757 ext. 7771
(c)
1998, 1999 Data Device Corporation
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Cbw
Rb
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Cbw/10 Rb Cbw Cbw/10
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V E L
RH RL BIT
V E L S J 2
S J 1
VEL2 VEL1
SHIFT
SYNTHESIZED REFERENCE
SIN -S
-
+S CONTROL TRANSFORMER GAIN DEMODULATOR D1 D0 D1 D0 16 BIT UP/DOWN COUNTER
+ + RV HYSTERESIS VCO & TIMING -VCO R CLK VEL
COS
-C
-
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2
+C
+
VDDP PCAP NCAP VSSP
-5 V INVERTER
AGND VDD GND VSS DATA LATCH
INTERNAL ENCODER EMULATION
R SET
INH BIT 1 - BIT 16
EM
EL
D1 D0
A QUAD B A U/B ZIP_EN
CB/ZIP
UP/DN
RD-19230 P-05/05-0
FIGURE 1. RD-19230 SERIES BLOCK DIAGRAM
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TABLE 1. RD-19230 SPECIFICATIONS
These specs apply over the rated power supply, temperature,and reference frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion. PARAMETER RESOLUTION FREQUENCY RANGE ACCURACY -XX2 (Note 3) -XX3 (Note 3) Repeatability Differential Linearity FREQUENCY RANGE ACCURACY -XX5 (Note 3) Repeatability Differential Linearity REFERENCE Type Voltage: differential single ended overload Frequency Input Impedance Common Mode Range SYNTHESIZED REFERENCE Sig/Ref Phase Shift Correction SIGNAL INPUT Type Voltage: operating overload Input impedance DIGITAL INPUTS (Note 10) TTL / CMOS COMPATIBLE INPUTS Inhibit (INH) Enable Bits 1 to 8 (EM) } Enable Bits 9 to 16 (EL) } Resolution and Mode Control (D1 & D0) (See Notes 1 & 2) UNIT Bits Hz minutes minutes LSB LSB Hz minutes LSB LSB VALUE 10, 12, 14, or 16 (Note 1 & 2) 1k - 4k 4 +1 LSB 2 +1 LSB 1 1 1k - 5k (Note 12) 1 +1 LSB 1 1
Vp-p Vp Vp Hz Vp deg
Vrms Vp
47-1k (Note 4) 4 +1 LSB 2 +1 LSB 1 1 47-1k (Note 4) 1 +1 LSB 1 1 (+RH, -RL) Differential 10 max. (Note 11) 5 max. (1.5 min.)(Note 11) 25 continuous; 100 transient DC to 10k (Note 12) 10M minutes. || 20 pf 3 (note 5) 45 max. from 400 Hz to 10kHz (+S, -S, SIN, +C, -C, COS) Resolver, differential, groundbased 2 15% 25 continuous 10M minutes || 10 pF.
4k - 10k 5 +1 LSB 3 +1 LSB 2 2
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Logic 0 = 0.8 V max. / Logic 1 = 2.0 V minutes. Loading=10 A max P.U. current source to +5 V || 5 pF max., CMOS transient protected Logic.comwithin 150 ns (Logic 1 = Transparent) 0 inhibits; Data stable { Logic 0 enables; Data stable within 150 ns (Logic 0 = Transparent) { Logic 1 = High Impedance; Data High Z within 100 ns (Note 8) Mode Resolver " " " LVDT " " " D1 0 0 1 1 -5 V 0 1 -5 V D0 0 1 0 1 0 -5 V -5 V -5 V Resolution 10 bits 12 bits 14 bits 16 bits (Preset, Note 10) 8 bits 10 bits 12 bits 14 bits
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ZIP_EN CMOS Compatible Inputs SHIFT
Notes:
Logic 0 enables ZIP, Logic 1 enables CB Logic 0 = 1.5 V max., Logic 1 = 3.5 V minutes., negative voltage = -3.5 V minutes. Logic 1 selects VEL1 components, Logic 0 selects VEL2 components
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1. As parallel resolution is reduced, pairs of bits are disabled. (Unused bits are set to a logic "0.") * 14 bit resolution: 15/16 disabled, * 12 bit resolution: 13/14, 15/16 disabled, * 10 bit resolution: 11/12, 13/14, 15/16 disabled 2. In LVDT mode, Bit 3 is the MSB and resolution is programmable to 8, 10, 12, and 14 bits. 3. Accuracy specification below for LVDT mode, null to + full scale travel (45 degrees) (2-wire configuration). 4 Minute part = 0.15% + 1 LSB of full scale "resolution set" 2 Minute part = 0.07% + 1 LSB of full scale "resolution set" 1 Minute part = 0.035% + 1 LSB of full scale "resolution set" Accuracy specification below for LVDT mode, full scale travel (90 degrees) (3-wire configuration). 4 Minute part = 0.07% + 1 LSB of full scale "resolution set" 2 Minute part = 0.035% + 1 LSB of full scale "resolution set" 1 Minute part = 0.017% + 1 LSB of full scale "resolution set" Note that these accuracy specifications are for the converter and do not consider any front end external resistor tolerances. 4. In the frequency range of 47Hz to 1kHz, there will be 1 LSB of jitter at quadrant boundaries. 5. The maximum phase shift tolerance will degrade linearly from 45 degrees at 400 Hz to 30 degrees at 60 Hz. 6. When using the -5V inverter, the VDD supply current will double and VSSP can be up to 20% low, or -4V. 7. || = in parallel with. 8. High Z refers to parallel data only. 9. Normal ESD (Electro Static Device) handling precautions should be observed. 10. Any unused pins may be left floating (unconnected). All TTL & CMOS input pins are internally pulled up to +5 Volts. 11. A signal less than 500 mV will assert BIT. 12. -XX5 accuracy is 1 minute + 1 LSB up to 5 kHz max. 13. For Ka definition, see the RDC-19220/RD-19230 application manual acceleration lag section.
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TABLE 1. RD-19230 SPECIFICATIONS (CONTINUED)
These specs apply over the rated power supply, temperature, and reference frequency ranges; 10% signal amplitude variation, and 10% harmonic distortion. PARAMETER CMOS Compatible Inputs (cont) UP/DN A QUAD B DIGITAL OUTPUTS Drive Capability UNIT VALUE Logic 0, precharged components gain is 4 Logic 1, precharged components gain is 1/4 Logic 0 enables encoder emulation, Falling edge latches encoder resolution 50 pF+ Logic 0: 1 TTL load, 1.6 mA at 0.4 V max. Logic 1; 10 TTL loads, = 0.4 mA at 2.8 V minutes. Logic 0; 100 mV max. driving CMOS Logic 1; +5 V supply minus 100 mV minutes. driving CMOS High Z; 10 A || 5 pF max. (Note 8) 10, 12, 14, or 16 parallel lines; natural binary angle positive logic (see note 2) 0.25 to 0.75 s positive pulse leading edge initiates counter update. (CB functions with ZIP_EN pin tied to +5 V or NC), Logic 1 at all 0's This output is active when the ZIP_EN pin is tied to GND (Logic 0). The BIT error is triggered if any of the following conditions exist: ~ 100 LSB's of error, Loss of Signal (LOS), or Loss of Reference (LOR) is less than 500 mVp, or a false null occurs when the phase detect circuitry causes a BIT and corrects the error. Logic 0 for fault condition. Incremental Encoder Output (at maximum bandwidth) 10 12 1152 288 1200 1200 5.7M 5.7M 19.5 19.5 295k 295k 2400 2400 .com 1200 1200 2M 500k 2 8
Parallel Data (1-16) Converter Busy (CB)
Zero Index Pulse (ZIP) Built-In-Test (BIT)
A, B DYNAMIC CHARACTERISTICS Resolution Tracking Rate (minutes) Bandwidth (Closed Loop) omKa(Acceleration Constant) Note 13 t4U.c A1 A2 A B Acceleration (1 LSB lag) Settling Time (179 step) VELOCITY CHARACTERISTICS Polarity Voltage Range (Full Scale) Scale Factor Error Scale Factor TC Reversal Error Linearity Zero Offset Zero Offset TC Load POWER SUPPLIES Nominal Voltage Voltage Range Max Volt. w/o Damage Current TEMPERATURE RANGE Operating (case) -30X -20X Storage Junction-to-Case Junction-to-Ambient Junction Temp Max MOISTURE SENSITIVITY LEVEL PHYSICAL CHARACTERISTICS Size: 64-pin Quad Flat Pack WEIGHT
bits rps Hz 1/sec2 1/sec 1/sec 1/sec 1/sec deg/sec2 msec
14 72 600 1.4M 4.9 295k 1200 600 30k 20
16 18 300 360k 1.2 295k 600 300 2k 50
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Positive for increasing angle 4 (at nominal power supply) V 10 typ 20 max % 100 typ 200 max PPM/C 0.75 typ 1.3 max % 0.25 typ 0.50 max % 5 typ 10 max mV 15 typ 30 max V/C 8 min k (note 6) V +5 (VDD) -5 (VSS) % 5 5 V +7 -7 mA 25 max. (each), 17 typ.* (* Typical current is when a 30K resistor is used for the current set.)
C C C C/W C/W C
0 to +70 -40 to +85 -65 to +150 20 50 150 Level 1 Tested in accordance with JEDEC SPEC J-STD-020
in(mm) oz(g)
0.52 x 0.52 (13.2 x 13.2) 0.018 ( 0.5 )
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THEORY OF OPERATION
The RD-19230 is a mixed signal CMOS IC containing analog input and digital output sections. Precision analog circuitry is merged with digital logic to form a complete high-performance tracking resolver-to-digital converter. For user flexibility and convenience, the converter bandwidth, dynamics, and velocity scaling are externally set with passive components. The RD-19230 Functional Block Diagram is shown in FIGURE 1. The analog conversion electronics require 5 VDC power supplies, and the converter contains a charge pump to provide the user with the option of a single-ended +5 VDC supply. The converter front-end consists of differential sine and cosine input amplifiers which are protected up to 25 V with 2 k resistors and diode clamps to the 5 VDC supplies. By performing the following trigonometric identity, SIN(COS) - COS(SIN) = SIN(-), the Control Transformer (CT) compares the analog input signals ( ) with the digital output ( ), resulting in an error signal proportional to the sine of the angular difference. The CT uses a combination of amplifiers, switches, logic and capacitors in precision ratios to perform the calculation. Note: The error output of the CT is normally sinusoidal, but in LVDT mode, it is triangular (linear) and can be used om to convert any linear transducer output. t4U.c
The converter accuracy is limited by the precision of the computing elements in the CT. Instead of a traditional precision resistor network, this converter uses capacitors with precisely controlled ratios. Sampling techniques are used to eliminate errors due to voltage drift and op-amp offsets. The error processing is performed using the industry standard technique for Type II tracking converters. The DC error is integrated yielding a velocity voltage which in turn drives a voltage controlled oscillator (VCO). This VCO is an incremental integrator (constant voltage input to position rate output) which, together with the velocity integrator, forms a Type II servo feedback loop. A lead in the frequency response is introduced to stabilize the loop and another lag at higher frequency is introduced to reduce the gain and ripple at the carrier frequency and above. The settings of the various error processor gains and break frequencies are done with external resistors and capacitors so that the converter loop dynamics can be easily controlled by the user.
TRANSFER FUNCTION AND BODE PLOT
The dynamic performance of the converter can be determined from its Transfer Function Block Diagrams and Bode Plots (open and closed loop). These are shown in FIGURES 2, 3, and 4.
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VEL
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B C BW /10 RV
VEL SJ1
VEL
-VCO 50 pf C VCO
CT RESOLVER INPUT () + GAIN DEMOD
R1 VCO 1 CS F S 11 mV/LSB 1.25 V THRESHOLD
-
16 BIT UP/DOWN COUNTER
H=1
DIGITAL OUTPUT ()
FIGURE 2. TRANSFER FUNCTION BLOCK DIAGRAM #1
VELOCITY OUT VCO A2 S DIGITAL POSITION OUT ()
ERROR PROCESSOR RESOLVER INPUT () + CT e
A1 S + 1 B S S +1 10B
H=1
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FIGURE 3. TRANSFER FUNCTION BLOCK DIAGRAM #2
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The open loop transfer function is as follows:
GENERAL SETUP CONDITIONS
A2 S +1 B Open Loop Transfer Function = 2 S +1 S 10B
( (
) )
(Note: For detailed application and technical information see the RDC-19220 & RD-19230 series converter applications manual (Document # MN-19220XX-001) which is available for download from the DDC web site at www-ddc-web.com.)
where A is the gain coefficient and A2=A1A2 and B is the frequency of lead compensation. The components of gain coefficient are error gradient, integrator gain, and VCO gain. These can be broken down as follows:
DDC has external component selection software which considers all the criteria below. In a simple fashion, it asks the key system parameters (carrier frequency, resolution, bandwidth, and tracking rate) needed to derive the external component values. The following recommendations should be considered when installing the RD-19230 R/D converter: 1) In setting the bandwidth (BW) and Tracking Rate (TR) (selecting five external components), the system requirements need to be considered. For the greatest noise immunity, select the minimum BW and TR the system will allow. Selecting a fBW that is too low relative to the maximum application tracking rate can create a spin-around condition in which the converter never settles. The relationship to insure against this condition is detailed in TABLE 2. Verify your system does not exceed this parts dynamic specs RATIO = RPS/BW. Perform this calculation and verify the ratio does not exceed TABLE 2.
- Error Gradient = 0.011 volts per LSB (CT + Error Amp + Demod with 2 Vrms input) - Integrator Gain = Cs Fs volts per second per volt 1.1 CBW - VCO Gain = 1 LSBs per second per volt 1.25 RV CVCO
where: Cs = 10 pF Fs = 67 kHz when R CLK = 30 k CVCO = 50 pF
and t4U.com bandwidth.
RV, RB, and CBW are selected by the user to set velocity scaling
TABLE 2. TRACKING / BW RELATIONSHIP .com RPS (MAX)/BW RESOLUTION
1 0.50 0.25 0.125 10 12 14 16
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(CRITICALLY DAMPED)
GAIN = 4 2A OPEN LOOP B A
-6 db
2) Power supplies are 5 VDC. For lowest noise performance it is recommended that a 0.1 F or larger cap be connected from each supply to ground near the converter package. When using +5V and -5V supplies to power the converter, pins 23, 24, 26 and 27 must be no connection.
(rad/sec) 10B
-1 2d b/o
(B = A/2)
ct
/oc
t
GAIN = 0.4
3) There are two internal ground planes to reduce noise to the analog input due to digital ground currents. The resolver inputs and velocity output are referenced to AGND. The digital inputs and outputs are referenced to GND. The AGND and GND pins must be tied together as close to the package as possible, or unstable results may occur. 4) This device has several high impedance amplifier inputs (+C, -C, +S, -S, -VCO, VEL SJ1, and VEL SJ2) that are sensitive to noise coupling. External components should be connected as close to the converter as possible.
f BW = BW (Hz) = 2A 2 2A
2A
CLOSED LOOP
(rad/sec)
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FIGURE 4. BODE PLOTS
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5) Setup of bandwidth and velocity scaling for the optimized critically damped case should proceed as follows:
rates, a higher internal counting rate must be programmed by setting RCLK to a value less than 30k. See TABLE 4 for the appropriate values. Select frequency/resolution from TABLE 4 then reference TABLE 3 for max tracking rate. The Rv resistor and an internal 50pF capacitor are configured as an integrating circuit that resets to zero after a count occurs in either direction. This circuit acts as a VCO with velocity as its input and CB as its output. The Rv resistor and an internal 50pF capacitor determine the maximum rate of the VCO. Rv must be chosen such that the maximum rate of the VCO is less than the maximum internal clock rate. Choose the tracking rate in accordance with TABLE 3 to insure this relationship. The rates shown in TABLE 3 are based on ~90% of the nominal internal clock rate. The relationship between the velocity voltage and the VCO rate is given by:
Velocity Voltage VCO Frequency = 1 (Rv x 50 pF x 1.25)
- Select the desired f BW (closed loop) based on overall system dynamics. - Select f carrier 3.5f BW - Select the applications tracking rate (in accordance with TABLE 3), and use appropriate values for R SET and R CLK - Compute Rv = Full Scale Velocity Voltage Tracking Rate (rps) x 2 resolution x 50 pF x 1.25 V 3.2 x Fs (Hz) x 108 Rv x (f BW)2
- Compute CBW (pF) =
- Where Fs = 67 kHz for R CLK = 30 K 100 kHz for R CLK = 20 K 125 kHz for R CLK = 15 K - Compute RB = - Compute CBW 10 0.9 CBW x f BW
As an example:
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Calculate component values for a 16-bit converter with 100Hz bandwidth, a tracking rate of 10 RPS and a full scale.com velocity of 4 Volts.
4V = 97655 10 rps x 216 x 50 pF x 1.25 V 3.2 x 67 kHz x 108 = 21955 pF 97655 x 100 Hz2
+5V
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- Rv =
- Compute CBW (pF) =
- Compute RB =
0.9 = 410 k 21955 x 10 -12 x 100 Hz
33 58 27
6) Using the -5V Inverter will eliminate the need for a -5 V supply. Refer to FIGURE 5 for the necessary connections.
+ 10 F/10V
VDD VDD VDDP PCAP
26
When using the built-in -5 V inverter, the maximum tracking rate should be scaled for a full-scale velocity output of 3.5 V max.
Notes: 1) Use of the -5 V inverter is not recommended for applications that require the highest BW and Tracking Rates. 2) When using the RD-19230FX with the -5V inverter, the negative velocity output voltage should be limited to -3.5 Volts. When performing tracking rate calculations this must be taken into consideration.
47 F/10V +
24 23 16 17
RD-19230
NCAP VSSP VSS * VSS
25 22
GND AGND
HIGHER TRACKING RATES AND CARRIER FREQUENCIES
Maximum tracking rate is limited by the velocity voltage saturation (nominally 4 V) and the maximum internal clock rate (nominally 1,333,333 Hz for R CLK = 30k). To achieve higher tracking
* Pin 16 has been renamed Vss since it will typically be connected to -5 VDC. Applications requiring a differential front-end configuration must connect this pin to Vss. Voltage follower mode can be implemented with pin 16 tied to Vss by making external connections between the output of the SIN/COS amplifiers and their respective inputs. When left unconnected, the RD-19230 will internally configure the front-end amplifiers in voltage follower mode.
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FIGURE 5. -5V INVERTER CONNECTIONS
RD-19230 P-05/05-0
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INPUT TRANSFORMERS
Refer to TABLE 5 to select the proper transformer for Reference, Synchro and Resolver inputs.
INPUT CONFIGURATION
The converter input can be configured using either transformers or thin film networks per the following tables and figures. Signal input configuration using thin film networks with a tolerance of 0.02% adds 1 LSB of additional error to accuracy. Signal input configuration using transformers adds 1 minute of additional error to accuracy.
TABLE 3. MAX TRACKING RATE (MINUTES) IN RPS
RC / RSET () 30k** or open 23k 23k RS / RCLK () 30k 20k 15k RESOLUTION 10 1152 1200 * 12 288 432 576 14 72 108 * 16 18 27 *
TABLE 4. CARRIER FREQUENCY (MAX) IN KHZ
RC / RSET () 30k** or open 23k 23k 23k RS/ RCLK () 30k 30k 20k 15k RESOLUTION 10 10 10 10 10 12 10 10 10 10 14 7 10 10 * 16 5 7 10 *
* Not recommended. ** The use of a high quality thin-film resistor will provide better temperature stability than leaving open. Note: RC "Rcurrent" = RSET t4U.com RS "Rsample" = RCLK
* Not recommended. ** The use of a high quality thin-film resistor will provide better temperature stability than leaving open. Note: RC "Rcurrent" = RSET RS "Rsample" = RCLK
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TABLE 5. TRANSFORMERS
P/N 52034 52035 52036 52037 52038 B-426 52039-X 24133-X TYPE S-R S-R R-R R-R R-R Reference Synchro Reference FREQUENCY (HZ)* IN (VRMS)* OUT (VRMS)** 400 400 400 400 400 400 60 60 11.8 90 11.8 26 90 115 90 115 2 2 2 2 2 3.4 2 3/6 **** ANGLE LENGTH (IN) WIDTH (IN) HEIGHT (IN) ACCURACY*** 1 1 1 1 1 N/A 1 N/A 0.81 0.81 0.81 0.81 0.81 0.81 1.1 1.125 0.61 0.61 0.61 0.61 0.61 0.61 1.14 1.125 0.3 0.3 0.3 0.3 0.3 0.32 .42 .42 FIGURE NUMBER 6 6 7 7 7 8 9 9
* 10% Frequency (Hz) and Line-to-Line input voltage (Vrms) tolerances ** 2 Vrms Output Magnitudes are -2 Vrms 0.5% full scale *** Angle Accuracy (Max Minutes) **** 3 Vrms to ground or 6 Vrms differential (3% full scale) Dimensions are for each individual main and teaser 60 Hz Synchro transformers are active (requires 15 Vdc power supplies) 400 Hz transformer temperature range: -55C to +125C 60 Hz transformer (52039-X, 24133-X) temperature ranges: add to part number -1 or -3, -1 = -55C to +85C -3 = 0 to +70C The following transformers can be ordered directly from DDC, Tel (631) 567-5600: P/N 52039-X, 24133-X The following transformers can be ordered directly from Beta Transformer Technology Corporation (BTTC), Tel (631) 244-7393: P/N 52034, 52035, 52036, 52037, 52038, and B-426.
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0.61 MAX (15.49) 0.61 MAX (15.49) 0.30 MAX (7.62) 0.09 MAX (2.29) 0.15 MAX (3.81) 0.15 MAX (3.81) 0.09 MAX (2.29)
1
345 T1A
11 12 T1B
14 15
0.81 MAX (20.57) 0.600 (15.24) 0.115 MAX (2.92)
10 9 8 7 6
20 19 18 17 16
SIDE VIEW
TERMINALS 0.025 0.001 (6.35 0.03) DIAM 0.125 (3.18) MIN LENGTH SOLDER PLATED BRASS Dimensions are shown in inches (mm).
0.100 (2.54) TYP TOL NON CUM
BOTTOM VIEW PIN NUMBERS FOR REF. ONLY
BOTTOM VIEW
T1A S1 1 5 S3 SYNCHRO INPUT T1B 11 16 -COS 3 10 +SIN RESOLVER OUTPUT 6 -SIN
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S2
15
20
+COS
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.com FIGURE 6. TRANSFORMER LAYOUT AND SCHEMATIC (SYNCHRO INPUT - 52034/52035)
0.61 MAX (15.49) 0.61 MAX (15.49) 0.30 MAX (7.62) 0.09 MAX (2.29) 0.15 MAX (3.81) 0.15 MAX (3.81) 0.09 MAX (2.29)
1
345 T1A
11 12 T1B
14 15
0.81 MAX (20.57) 0.600 (15.24) 0.115 MAX (2.92)
10 9 8 7 6
20 19 18 17 16
SIDE VIEW
TERMINALS 0.025 0.001 (6.35 0.03) DIAM 0.125 (3.18) MIN LENGTH SOLDER PLATED BRASS Dimensions are shown in inches (mm).
0.100 (2.54) TYP TOL NON CUM
BOTTOM VIEW PIN NUMBERS FOR REF. ONLY
BOTTOM VIEW
T1A S1 1 6 -SIN
S3 RESOLVER INPUT
3
10
+SIN RESOLVER OUTPUT
T1B S4 11 16 -COS
S2
15
20
+COS
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FIGURE 7. TRANSFORMER LAYOUT AND SCHEMATIC (RESOLVER INPUT - 52036/52037/52038)
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CASE IS BLACK AND NON-CONDUCTIVE 1.14 MAX (28.96) 0.25 (6.35) MIN.
0.32 MAX (8.13)
0.61 MAX (15.49) 0.125 MIN (3.17) 0.09 MAX (2.29) 0.15 MAX (3.81)
*
S3
*
S1
*
+15 V (+15 V)
*
+S (-R)
+
*
*
* *
1.14 MAX (28.96)
52039 or 24133
0.85 0.010 (21.59 0.25)
123 T1A
5 0.600 0.81 MAX (15.24) (20.57)
(RH) S2 (RL) +
*
*
(V) V
(+R) +C
(-Vs) -Vs
*
*
*
0.13 0.03 (3.30 0.76)
10 9 8 7 6 0.105 (2.66)
SIDE VIEW TERMINALS 0.025 0.001 (6.35 0.03) DIAM 0.125 (3.18) MIN LENGTH SOLDER-PLATED BRASS Dimensions are shown in inches (mm).
Input RH
(BOTTOM VIEW)
0.42 (10.67) MAX.
0.100 (2.54) TYP TOL NON CUM
BOTTOM VIEW
0.175 0.010 (4.45 0.25) NONCUMULATIVE TOLERANCE
0.21 0.3 (5.33 0.76) 0.040 0.002 DIA. PIN. SOLDER PLATED BRASS
+15 V
+15 V
Output +R (RH) 24133 -R (RL)
Input S1 S2 S3 52039
Output +S +C
RL
1 INPUT 5
6 OUTPUT 10
V (Analog Gnd)
-Vs (-15 V)
V (Analog Gnd)
-Vs (-15 V)
The mechanical outline is the same for the synchro input transformer (52039) and the reference input transformer (24133), except for the pins. Pins for the reference transformer are shown in parenthesis ( ) below. An asterisk * indicates that the pin is omitted.
FIGURE 8. TRANSFORMER LAYOUT AND SCHEMATIC (REFERENCE INPUT - B-426) t4U.com
TYPICAL INPUTS FIGURES 10 through 14 illustrate typical input configurations.
EXTERNAL REFERENCE LO HI 1 B-426 5
RL RH
FIGURE 9. 60 HZ SYNCHRO AND REFERENCE TRANSFORMER DIAGRAMS (SYNCHRO INPUT - 52039 / REFERENCE INPUT - 24133) DataShee
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6 10
RESOLVER INPUT OPTION
S1 S3 S4 S2 1 TIA 3 11 TIB 15 16 52036(11.8V) OR 52037(26V) OR 52038(90V) 6 20 10
-S
+S
SIN
-R
+R
+C -C COS AGND
RD-19230
GND
OR
RL
RH
SYNCHRO INPUT OPTION
S1 S3 1 3 5 11 S2 15 TIB 10 TIA 6 20 +C +S
Note: The external BW components as shown in Figures 1 and 2 are necessary for the R/D to function.
16 52034(11.8V) OR 52035(90V)
FIGURE 10. TYPICAL TRANSFORMER CONNECTIONS
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EXTERNAL REF LO HI
R1 R3
R2 R4
See Note 3.
+S -S SIN COS -C
RL
RH
S3 S1
S4
S2
See Note 3.
+C A GND GND
Note: The external BW components as shown in Figures 1 and 2 are necessary for the R/D to function.
RESOLVER
1) Resistors selected to limit Vref peak to between 1.5 V and 5 V. 2) External reference LO is grounded, then R3 and R4 are not needed, and -R is connected to GND. 3) 10k ohms, 1% series current limit resistors are recommended.
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FIGURE 11. TYPICAL CONNECTIONS, 2 V RESOLVER, DIRECT INPUT .com
ee DataSh
S3
R1 R2
+S
-S
SIN
S1
S2
R1 R2
+C
Note: The external BW components as shown in Figures 1 and 2 are necessary for the R/D to function.
S4
A GND GND -C COS
2 R2 = X Volt R1 + R 2 R1 + R2 should not load the Resolver; it is recommended to use an R2 = 10 k R1 + R2 Ratio errors will result in Angular errors,
2 cycle, 0.1% Ratio error = 0.029 Peak Error.
FIGURE 12. TYPICAL CONNECTIONS, X- VOLT RESOLVER, DIRECT INPUT
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SIN 3 S1 S3 1 6
Ri Ri
Rf
-S 2 +S 5 +
Examples of Component Calculations: (1) 2V in, need gain of 1, use 10k for R1 &R2 Gain = RF Ri (2) 4V in, need gain of 0.5, Ri = 20k, Rf = 10k To Calculate Ri: Select 10k for Rf Ri = Rf x 0.5 (input L-L volt) Ri = 10k x 0.5 x (L-L volt)
Rf
RESOLVER INPUT A GND 4 COS 13
S4 S2
16 7
Ri Ri
8 10
Rf
-C 15 +C + Note: The external BW components as shown in Figures 1 and 2 are necessary for the R/D to function.
Rf
12 CONVERTER
S1 and S3, S2 and S4, and RH and RL should be ideally twisted shielded, with the shield tied to GND at the converter. For DDC-49530: Ri = 70.8 K, 11.8 V input, synchro or resolver. For DDC-49590: Ri = 270 K, 90 Volt input, synchro or resolver. Maximum additional error is 1 minute. Ri When using discrete resistors: Resolver L-L voltage = Rf x 2 Vrms, where Rf 6 k. For 2V direct input, use 10k matched resistors for Ri and Rf. Input options affect DC offset gains and therefore carrier frequency ripple and jitter. Offset gains associated with differential mode (offset gain for differential configuration = 1+Rf/Ri) and direct mode (offset gain for direct configuration = 1) show differential mode will always be higher. Higher DC offsets cause higher carrier frequency ripple due to the demodulation process. This carrier frequency ripple rides on top of the DC error signal, causing jitter. A higher carrier frequency versus bandwidth ratio will help to decrease ripple and jitter associated with offsets. In summary, R/Ds with differential inputs are more susceptible to offset problems than R/Ds in single-ended mode. R/Ds in higher resolutions, such as 16 bit, will further compound offset issues due to higher internal voltage gains. Although the differential configuration has a higher DC offset gain, the differential configuration's common mode noise rejection makes it the preferred input option. The tradeoffs should be considered on a design to design basis.
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SIN 3 S1 S3 1 6
Ri Ri
Rf
-S 2 +S 5 + Note: The external BW components as shown in Figures 1 and 2 are necessary for the R/D to function.
Rf
SYNCHRO INPUT 16 7 9 A GND 4 COS 14
Ri Ri Ri /2
8 15
Rf / 3
-C 15 +C 10 Rf / 3 11 +
S2
CONVERTER
S1, S2, S3 should be triple twisted shielded; RH and RL should be twisted shielded; In both cases the shield should be tied to GND at the converter. 11.8 Volt input = DDC-49530: Ri = 70.8 K, 11.8 V input, synchro or resolver. 90 Volt input = DDC-49590: Ri = 270 K, 90 Volt input, synchro or resolver. Maximum additional error is 1 minute using recommended thin film package. R When using discrete resistors: Resolver L-L voltage = i x 2 Vrms, where Rf 6 k Rf
FIGURE 14. SYNCHRO INPUT, USING DDC-49530/57470 (11.8 V), DDC-49590 (90 V) OR DDC-73089 (2V) .com
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DC INPUTS
As noted in TABLE 1, the RD-19230 accepts DC inputs. DC input operation is from 0 to 180 or 180 to 359 only, due to the possibility of an unstable false null, i.e., 180 hangup. The false null condition will only happen on power up and an instantaneous 180 step, therefore once the converter moves it will go to the correct answer. In real world applications where an instantaneous 180 change is impossible, the converter will always be correct within 360. The problem arises at power up in real systems. If the converter powers up at exactly 180 from the applied input, the converter will not move. This is very unlikely, although it is theoretically possible. This condition is most often encountered during wraparound verification tests, simulations, or troubleshooting. It is recommended that the synthesized reference option be disabled for DC input operation. Disable the synthesized reference by connecting pin 52, DSR, to ground through a 10 ohm resistor. The reference input is set to DC by tying RH to +5V and RL to ground or -5V. Set the COS and SIN inputs such that the maximum signal is equal to 1.8VDC. For example, at 90 the SIN input should equal t4U.com to 1.8VDC. This will keep the BW hysteresis consistent with AC operation. Input offsets will affect accuracy. Verify the COS and SIN inputs do not have DC offsets. If offsets are present, a differential op amp configuration can be used to minimize differential offset problems.
When operating with DC inputs the converter BIT will remain at Logic 0. Choose the bandwidth value of the converter based on the rate of change of the systems input amplitude variation. It should be large enough to minimize it's effect on the system dynamics. Note that if the bandwidth is too high the system will be more susceptible to noise. The accuracy of a converter using a DC input will be degraded from the rated accuracy. Consider the best case where the input is single ended and no additional DC offsets are present on the input of the converter - the accuracy will degrade by about 2 arc minutes. For example, if a part is rated at 2 arc minutes, a DC input will degrade the accuracy to approximately 4 arc minutes.
VELOCITY TRIMMING
The RD-19230 specifications for velocity scaling, reversal error, and offset are listed in TABLE 1. Velocity scaling and offset are externally trimmable for applications requiring tighter specifications than those available from the standard unit. FIGURE 15 shows the setup for trimming these parameters with external pots. It should also be noted that when the resolution is changed, ee DataSh velocity scaling is also changed.
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OPTIONAL BANDWIDTH COMPONENTS
The RD-19230 provides the option of using a second set of bandwidth components. The second set of components can be used for switch-on-the-fly or dual-bandwidth applications. The SHIFT and UP/DN inputs are used when switching bandwidth components, and their operation is described below. Refer to the block diagram, FIGURE 1.
+5 V -VCO 2
SHIFT
The SHIFT pin is an input that chooses between the VEL1 and VEL2 bandwidth components. This pin has an internal pull-up to +5V. When the SHIFT pin is left open, or a logic 1 is applied, the VEL1 components are selected. When a Logic 0 is applied, the VEL2 components are selected. The deselected set of bandwidth components are driven by an amplifier, with programmable gain, that follows the velocity amplifier. This amplifier can be used to precharge the deselected set of components to the voltage level that is expected after a change in resolution. (See description on BENEFIT OF SWITCHING RESOLUTION ON THE FLY.)
100 RV
100 k (OFFSET) -5 V
0.8 R V
RD-19230
0.4 RV (SCALING)
VEL 1
FIGURE 15. VELOCITY TRIMMING
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TABLE 6. PRECHARGE AMPLIFIER GAIN PROGRAMMING
UP/DN Logic 0 Logic 1 -5 V GAIN 4 1/4 1 FUNCTION preset resolution to increase preset resolution to decrease dual bandwidth
When this system type does not use the switch resolution on the fly implementation, large errors and increased settling times result. The errors exceed 100 LSBs causing the BIT to flag for a fault condition.
SWITCH ON THE FLY IMPLEMENTATION
The following steps detail switching resolution on the fly. For additional information refer to the Application Note #AN/MFT-3 "SWITCHING RESOLUTIONS ON THE FLY" available on the DDC web site at www.ddc-web.com. 1) The SHIFT pin should be controlled synchronously with the change in resolution. When shift is logic high, the VEL1 components will be selected. When shift is logic 0, the VEL2 components will be selected. 2) The second set of BW components (CBW2, RB2, CBW2/10) should typically be of the same value as the first set (CBW1, RB1, CBW1/10,) and should be installed on VEL2 and VEL SJ2.
UP/DN
The UP/DN input selects the gain of the amplifier driving the deselected set of bandwidth components. UP/DN has three input states. See TABLE 6 to relate input to gain.
BENEFIT OF SWITCHING RESOLUTION ON THE FLY
Switching resolution on the fly can be used in applications that require high resolution for accurate position control, and tracking rates or settling times that are faster than the high resolution mode will allow.
Note: Each set of bandwidth components must be chosen to The RD-19230 can track four times faster for each step down in insure that the tracking rate to BW ratio (listed in resolution (i.e., a step from 16 bits to 14 bits). The velocity output TABLE 2) is not exceeded for the resolution in which will be scaled down by a factor of four with each step down in it will be used. resolution. For example, if the velocity output is scaled such that 4 3) The UP/DN line programs the gain of the precharged compot4U.com Volts = 10 RPS in 16 bit resolution, then the same converter Shee will output 1 Volt for 10 RPS in 14 bit resolution. To avoid glitchnents/amplifier. If the resolution is increasing (UP/DN logic 0), Data es in the velocity output, the second set of bandwidth compothe gain .com of the precharge amplifier is set to four. If the resolunents can be precharged to the expected voltage, and switched tion is decreasing (UP/DN logic 1), the gain of the precharge in using the SHIFT input at the same time the resolution is amplifier is set to 1/4. The gain of the precharge amplifier changed. This will allow for a smooth velocity transition, resulting should be programmed prior to switching the resolution of the in reduced errors and minimal settling time after the change. converter, allowing enough time for the components to settle to the precharged level. This time will depend on the time conFIGURE 17 shows the way the converter behaves during a stant of the bandwidth components being charged. If switchchange in resolution while tracking at a constant velocity. The ing is limited to two adjacent resolutions (i.e., 14 and 16) then first illustration shows the benefits of switching in precharged the precharge amplifier can be set up to continuously maintain components while changing resolution. The second illustration the appropriate velocity voltage on the deselected composhows the result without the benefits of switching on the fly. nents, resulting in the fastest possible switching times. See The signals that have been recorded are: 1) VEL: velocity output pin on the RD-19230 2) ERROR: this is the analog representation of the error between the input and the output of the RD-19230 3) D0: an input resolution control line to the RD-19230 4) BIT: built-in-test output pin of the RD-19230 When this system uses the switch resolution on the fly implementation, the velocity signal immediately assumes the precharged level of the second set of components, resulting in small errors and reduced settling times. Notice that the BIT output in FIGURE 17, does not indicate a fault condition.
CONTROL D0 58 27 SHIFT UP/DN +5V D1
RD-19230
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FIGURE 16. INPUT WIRING - SWITCHING ON THE FLY BETWEEN 14 AND 16 BIT RESOLUTION
RD-19230 P-05/05-0
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FIGURE 16 for an example of the input wiring connections necessary for switching on the fly between 14 and 16 bit resolution.
INHIBIT, ENABLE, AND CB TIMING
The Inhibit (INH) signal is used to freeze the digital output angle in the transparent output data latch while data is being transferred. Application of an Inhibit signal does not interfere with the continuous tracking of the converter. As shown in FIGURE 18, angular output data is valid 150 ns maximum after the application of the negative inhibit pulse. Output angle data is enabled onto the tri-state data bus in two bytes. Enable MSBs (EM) is used for the most significant 8 bits and Enable LSBs (EL) is used for the least significant 8 bits. As shown in FIGURE 19, output data is valid 150 ns maximum after the application of a negative enable pulse. The tri-state data bus returns to the high impedance state 100 ns maximum after the rising edge of the enable signal. The Converter Busy (CB) signal indicates that the tracking converter output angle is changing 1 LSB. As shown in FIGURE 20, output data is valid 50 nS maximum after the middle of the CB pulse. CB pulse width is 1/40 FS, which is nominally 375 ns.
INHIBIT
DUAL BANDWIDTHS
With the second set of BW component pins, the user can set two bandwidths for the RD-19230 and choose between them. To use two bandwidths, proceed as follows: 1) Tie UP/DN to pin -5V. 2) Choose the two bandwidths following the guidelines in the General Setup Considerations; the RV resistor must be the same value for both bandwidths. 3) Use the SHIFT pin to choose between bandwidths. A logic 1 selects the VEL1 components and a logic 0 selects the VEL2 components. With Switch Resolution on the Fly Implemented
0V
VEL
-5V
150 nsec max
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ERROR
0
DATA
DATA VALID
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5V
FIGURE 18. INHIBIT TIMING
ENABLE
D0
0V
5V
BIT
0V
150 nsec MAX DATA VALID
100 nsec MAX
ERROR = 13.6 LSBs per box Depending on the bandwidth, the step error may be greater. Also, less velocity / movement will lessen the error glitch. The graphs above shows a worst case condition based on one bandwidth and tracking rate setup. Worst case is when the velocity overshoot hits the saturations point.
DATA
HIGH Z
HIGH Z
For 16-bit bus, EM/EL may be tied to ground for transparent mode, as long as only 1 R/D channel is used on the data bus.
Without Switch Resolution on the Fly Implemented
0V
FIGURE 19. ENABLE TIMING
250 to 750 nsec CB
VEL
-5V
ERROR
0
50 nsec
5V
DATA
DATA VALID
DATA VALID
D0
0V
FIGURE 20. CONVERTER BUSY TIMING
Note: The converter INH may be applied regardless of the CB line state. If the CB is busy the converter INH will wait for timing referenced to CB (Fig.20), before setting the INH latch. Therefore when applying an inhibit signal to the converter there is no need to monitor the CB line. RD-19230 P-05/05-0
5V
BIT
0V
ERROR = 1500 LSBs per box
FIGURE 17. BENEFIT OF SWITCHING RESOLUTION ON THE FLY .com
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INTERNAL ENCODER EMULATION
The RD-19230 can be programmed to encoder emulation mode by toggling the A_QUAD_B input to a logic 0. The U/B output pin becomes B (LSB XOR LSB + 1). The A (LSB + 1) and B output signals can be used in control systems that are designed to interface with incremental optical encoders. To enable the Zero Index pulse, ZIP_EN should be tied to a logic 0. An example circuit to create a low going edge of A_QUAD_B is depicted in Figure 23B. If the power supply takes longer than 50ms to start up then the time constant of 50ms set in FIGURE 23B must be extended. Alternatively a system logic reset signal or internally generated logic `load' pulse can be generated to latch in the encoder resolution. The resolution of the incremental outputs is latched from the D0 and D1 inputs on the low going edge of A_QUAD_B. The resolution of the parallel data outputs may be changed any time after the encoder resolution is latched (see FIGURE 23).
CLARIFICATION OF A_QUAD_B, U/B AND ZIP_EN FUNCTIONS
The RD-19230 is a tracking converter which is designed with a Type II closed servo loop. The Type II closed servo loop has an internal incremental integrator. This integrator acts as an updown position counter. An AC error (e) within the RD-19230 represents the difference between (current angle to be digitized) and (the angle stored in digital form in the up-down counter). Because the RD-19230 constitutes in itself a Type II closed loop servomechanism, it continuously attempts to null the error to zero. This is accomplished by counting up or down 1 LSB until is equal to thus having an error of zero.
TABLE 7. A_QUAD_B (PIN 30) FUNCTION
A_QUAD_B (PIN 30) 0 1 U/B (PIN 29) B U
TABLE 8. ZIP_EN (PIN 55) FUNCTION
ZIP_EN (PIN 55) CB/ZI (PIN 31)
When in A_QUAD_B mode, the resolution of the parallel data 0 ZI can be changed to a resolution equal to or greater than the 1 CB A_QUAD_B resolution setting only. For example if the When A_QUAD_B is logic 0, encoder emulation mode is selectA_QUAD_B mode is active and the resolution is set to 12 bits, om resolution of the parallel programmed data can be changed the ed (i.e. The U/B output [Pin 29] is programmed to B). The t4U.c Shee from 12 bits to 14- or 16-bits by setting D0 & D1. If 10-bit mode encoder emulator resolution is set on the falling edge of Data is required for the parallel data, the A_QUAD_B resolution must A_QUAD_B (see TABLE 7). .com also be programmed to 10-bits. When A_QUAD_B is logic 1, encoder emulation mode is not selected (i.e. The U/B output is set to U, which indicates the Note: The encoder resolution must be less than or equal to direction of the internal position counter). the resolution of the parallel data outputs. Refer to FIGURE 21. Note: U indicates the "UP" direction of the counter. If the RD19230 is at a static angle awaiting a new angle , U indiThe timing of the A, B and ZIP (or North Reference Pole [NRP]) cates the direction the counter was going to get to the output is dependent on the rate of change of the current angle . As the error is approaching zero, the synchro/resolver position (rps or degrees per second) and the internal analog circuitry voltage may overshoot before encoder resolution latched into the RD-19230 (refer to settling - which would then indicate an incorrect direcFIGURE 22). The calculations for the timing are: tion. Because of this overshoot, the U output should not be relied on after settling to a static state. Only durn = resolution of parallel data ing active resolver movement will the U output state be reliable. U is a logic 1 when going in the positive direct = 1 / ( 2n* Velocity(RPS)) tion (increasing angle). It is a logic 0 when going in the negative direction (decreasing angle). T = 1 / ( Velocity(RPS)) Note: The Z1 pulse is high when all the bits of the counter are zero. If the resolution of the counter, (parallel data) is programmed differently than that of the A_QUAD_B then the resolution of the counter will determine the resolution of the ZIP. ZIP_EN chooses between the CB and Zero Index pulse outputs and is independent of encoder emulation mode. A logic 1 enables the CB pulse, a logic 0 enables the Zero Index pulse (see TABLE 8). Note: When the RD-19230FX is set for 16-bit mode, the LSB is bit 16. When the RD-19230FX is set for 14-bit mode, the LSB is bit 14 and bits 15 and 16 are set to logic "0". (See TABLE 1, NOTE 1).
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RD-19230
1 MSB 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BIT 16 LSB
SYNTHESIZED REFERENCE
The synthesized reference section of the RD-19230 eliminates errors due to phase shift between the reference and signal inputs. Quadrature voltages in a resolver or synchro are by definition the resulting 90 fundamental signal in the nulled out error voltage (e) in the converter. Due to the inductive nature of synchros and resolvers, their output signals lead the reference input signal (RH and RL). When an uncompensated reference signal is used to demodulate the control transformer's output, quadrature voltages are not completely eliminated. As shown in the block diagram, FIGURE 1, the converter synthesizes its own internal reference signal based on the SIN and COS signal inputs. Therefore, the phase of the synthesized (internal) reference is determined by the signal input, resulting in reduced quadrature errors.
1 0
1 2
1 4
1 6
A
B
FIGURE 21. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
B(X- or LSB & LSB+1) 2t
BUILT-IN-TEST (BIT)
The BIT output is active low, and is triggered if any of the following conditions exist: 1) Loss of Signal (LOS) - SIN and COS inputs both less than 500mV.
t
A (LSB+1)
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ZIP (NRP)
D 2) Loss of Reference (LOR) - Reference Input less than 500 mV. ata
Shee
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0
T
359.95
D0/D1
DATA VALID 50 nsec
A QUAD B
demodulator output, which is proportional to the difference between the analog input and digital output. When it exceeds approximately 100 LSBs (in the selected resolution), BIT will be asserted. This condition can occur any time the analog input changes at a rate in excess of the maximum tracking rate. During power up, the converter may see a large difference between the SIN/COS inputs and the digital output angle held in its counter. BIT will be asserted until the converter settles within ~ 100 LSB's of the final result.
FIGURE 23A. TIMING FOR INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
+5V
A quad B
4) 180 phase error input signal to reference input (false null) causes a BIT plus kickstarts the converter counter to correct the error. The LOS has a filter on it to filter out the reference. Since the lowest specified reference frequency is 47 Hz (~21 ms), the filter must have a time constant long enough to filter this out. Time constants of 50 ms or more are possible. A 500 s dynamic delay occurs before the error BIT becomes active. This dynamic delay is responsive to the active filter loop.
C R
~ = RC
(ie. 50ms = 50Kohms x 1f)
FIGURE 23B. EXAMPLE CIRCUIT FOR A QUAD B RESET .com
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LVDT MODE
As shown in TABLE 1, the RD-19230 unit can be made to operate as an LVDT-to-digital converter. In this mode the RD-19230 functions as a ratiometric tracking linear converter. When linear AC inputs are applied from a LVDT the converter operates over one quarter of its range. This results in two less bits of resolution for LVDT mode than are provided in resolver mode. LVDT output signals need to be scaled to be compatible with the converter input. FIGURE 25 is a schematic of an input scaling circuit applicable to 3-wire LVDTs. The value of the scaling constant "a" is selected to provide an input of 2 Vrms at full stroke of
the LVDT. The value of scaling constant "b" is selected to provide an input of 1 Vrms at null of the LVDT. Suggested components for implementing the input scaling circuit are a quad op-amp, such as a OP11 type, and precision thin-film resistors of 0.1% tolerance. FIGURE 24 illustrates a 2-wire LVDT configuration. Data output of the RD-19230 is Binary Coded in LVDT mode. The most negative stroke of the LVDT is represented by ALL ZEROS and the most positive stroke of the LVDT is represented by ALL ONES. The most significant 2 bits (2 MSBs) may be used as overrange indicators. Positive overrange is indicated by code "01" and negative overrange is indicated by code "11" (see TABLE 9).
TABLE 9. 12-BIT LVDT OUTPUT CODE FOR FIGURE 25
LVDT OUTPUT OVER RANGE MSB DATA xxxx 1111 0000 0000 0000 1111 0000 0000 xxxx xxxx 1111 0000 0001 0000 1111 0000 0000 xxxx LSB
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+ over full travel 01 xxxx + full travel -1 LSB 00 1111 +0.5 travel 00 1100 +1 LSB 00 1000 null 00 1000 - 1 LSB 00 0111 -0.5 travel 00 0100 .com - full travel 00 0000 - over full travel 11 xxxx
ee DataSh
C1
SIN
aR 2 WIRE LVDT REF IN R R C2 aR
COS -S -
R
+
+S
FS = 2 V
bR
R R 2R
R
-
-C
2R 2V R
+C
R bR
+
C1 = C2, set for phase lag = phase lead through the LVDT.
+RH -RL
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FIGURE 24. 2-WIRE LVDT DIRECT INPUT
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aR
VB
R R aR
SIN + -S
FS = 2V
R' R'
+S
REF
R
bR 2R' R'
COS -C
R
VA
+
R/2 bR
-2V
2R'
R'
+C +RH -RL
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Notes: 1. R' > 10 k 2. Consideration for the value of R is LVDT loading. 3. RMS values given. 4. Use the absolute values of Va and Vb when subtracting per the formula for calculating resistance values, .com and then use the calculated sign of "Va and Vb" for calculating SIN and COS. The calculations shown are based upon full scale travel being to the Va sideof the LVDT. 5. See the RDC application manual for calculation examples. 6. Negative voltages are 180 degrees phase from reference.
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b=
LVDT OUTPUT
a=
1=1 VAnull VBnull 2 (VA - VB) max
RD-19230 INPUT 2V 1V
SIN
VA VB +FS NULL -FS
COS = -1V - a (VA - VB) 2 SIN = -1V + a (VA - VB) 2
COS -FS NULL +FS
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Data Device Corporation www.ddc-web.com
FIGURE 25. 3-WIRE LVDT SCALING CIRCUIT & CALCULATIONS
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TABLE 10. RD-19230 PINOUTS
# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VEL -VCO SJ1 SJ2 SHIFT VEL2 TP1 (test point) VEL1 TP2 (test point) +C COS -C +S SIN -S VSS (-5V) NAME # 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NAME VSS (-5V) TP3 (test point) R CLK R SET ENM AGND VSSP NCAP GND PCAP VDDP BIT U/B A_QUAD_B CB (ZI) Bit 1 (MSB) # 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 N/C Bit 9 Bit 2 Bit 10 Bit 3 Bit 11 Bit 4 N/C Bit 12 Bit 5 Bit 13 Bit 6 Bit 14 Bit 7 Bit 15 NAME VDD (+5V) # 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Bit 8 Bit 16 (LSB) A (LSB + 1) DSR N/C N/C ZIP_EN TP6 (test point) ENL VDD (+5V) UP/DN D0 D1 INH RH RL NAME
NOTES: 1. See FIGURE 5 for +5 V only operation. 2. Unless otherwise specified, pins TP1 through TP4 are for factory use only, and should be left unconnected.
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32 17 0.096MAX (2.45MAX) 33 16 0.0098MIN,0.0197MAX (0.25MIN,0.50MAX) 0.5200.010 (13.20.25)
RD - 1 9 2 3 0 F X -XXX Date C o d e
0.078+0.004 -0.002 (2.00+0.10 ) -0.05
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0.0197 (0.50)
*
0.3940.004 (10.000.10)
48
pin1
0.0098MIN,0.0197MAX (0.25MIN,0.50MAX)
49
64
0.096MAX (2.45MAX)
*
0.3940.004 (10.000.10)
0.007MAX (0.17MAX)
0.008 (0.22) 0.035+0.006 -0.004 ( 0.88+0.15 ) -0.10
0.5200.010 (13.20.25)
Dimensions shown are in inches (millimeters). Mechanical Design done in millimeters.
*
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Data Device Corporation www.ddc-web.com
DIMENSIONS SHOWN ARE TO DOTTED LINES
FIGURE 26. RD-19230 MECHANICAL OUTLINE (PLASTIC PACKAGE)
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THIN-FILM RESISTOR NETWORKS FOR MOTION FEEDBACK PRODUCTS
DDC converters such as the RDC-19220/2S and RD-19230 require closely matched 2Vrms SIN/COS input voltages to minimize digital error. DDC has custom thin-film resistor networks that provide the correctly matched 2Vrms converter outputs for 11.8Vrms Resolver/Synchro or 90Vrms synchro applications. Any imbalance of the resistance ratio between the SIN/COS inputs will create errors in the digital output. DDC's custom thinfilm resistor networks have very low imbalance percentages. The networks are matched to 0.02%, which equates to 1 LSB of error for a 16-bit application.
FIGURE 27. THIN-FILM RESISTOR NETWORKS
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TABLE 11. THIN-FILM RESISTOR NETWORKS
THIN FILM RESISTOR NETWORK DDC-55688-1 DDC-49530 DDC-57470 DDC-49590 DDC-73089 DDC-57471 INPUT VOLTAGE (VRMS) 2 Single Ended 11.8 11.8 90 2 Differential 90 OUTPUT VOLTAGE (VRMS) 2 2 2 2 2 2 PACKAGE TYPE Ceramic DIP Plastic DIP Surface Mount Ceramic DIP Surface Mount Surface Mount
Notes: 1. For thin-film network specifications see the "Thin-Film Network Specifications for Motion Feedback Products" Data Sheet available from the DDC web site. 2. Operating temperature range is -55C to +125C.
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Data Device Corporation www.ddc-web.com 21 RD-19230 P-05/05-0
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ORDERING INFORMATION
RD-19230FX-X X X X Supplemental Process Requirements: T = Tape and Reel (note 1) (50 pc. minimum order) Accuracy: 2 = 4 minutes + 1 LSB 3 = 2 minutes + 1 LSB 5 = 1 minutes + 1 LSB (maximum reference frequency = 5 kHz) Reliability: 0 = Standard DDC Procedures Operating Temperature Range: 2 = -40 to +85C 3 = 0 to +70C Package Options: X = Standard G = Lead Free
Notes: 1) DDC does not recommend Tape and Reel due to potential lead damage.
COMPONENT SELECTION SOFTWARE: Component selection software can be downloaded from our web site at www.ddc-web.com Evaluation Card Available P/N RD19230EX-300 (See the DDC web site for this card's User's Guide)
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STANDARD DDC PROCESSING FOR PLASTIC.com MONOLITHIC PRODUCTS
TEST INSPECTION / WORKMANSHIP ELECTRICAL TEST MIL-STD-883 METHOD(S) 2017 DDC ATP CONDITION(S) -- --
The information in this data sheet is believed to be accurate; however, no responsibility is assumed by Data Device Corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. Specifications are subject to change without notice. Please visit our web site at www.ddc-web.com for the latest information.
105 Wilbur Place, Bohemia, New York, U.S.A. 11716-2482 For Technical Support - 1-800-DDC-5757 ext. 7771 Headquarters, N.Y., U.S.A. - Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. - Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. - Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland - Tel: +353-21-341065, Fax: +353-21-341568 France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22 Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide Web - http://www.ddc-web.com
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P-05/05-0 22
DATA DEVICE CORPORATION REGISTERED TO ISO 9001:2000 FILE NO. A5976
PRINTED IN THE U.S.A.
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